
According to foreign media reports, semiconductor foundry leader TSMC and AI chip giant NVIDIA are currently collaborating on testing TSMC's latest A16 process. NVIDIA may have already secured exclusive access to A16 production capacity.
The A16 process leverages nanosheet transistors and Super Power Rail (SPR) technology. Compared with the N2P process, A16 delivers 8–10% higher performance at the same power, reduces power consumption by 15–20%, and increases chip density by 7–10%. Volume production is planned for the second half of 2026. NVIDIA is expected to use A16 to manufacture its next-generation Feynman GPU architecture, slated for release in 2028.
A16 also imposes higher demands on advanced GPU packaging, requiring more Through-Silicon Vias (TSVs) for improved interconnectivity and thermal management. Advanced packaging technologies, particularly TSMC's CoWoS, have become a key bottleneck in AI chip production. NVIDIA's significant access to TSMC's CoWoS capacity—reportedly 70% of CoWoS-L annual capacity in 2025—gives it a substantial advantage in the AI chip race. Meanwhile, the tight CoWoS capacity has created opportunities for outsourced packaging and testing services as well as equipment makers.
To alleviate the CoWoS bottleneck, TSMC is actively developing alternatives, including CoPoS and planned wafer-level packaging, supported by new equipment and partner collaborations to meet growing market demand.
HBM supply also affects AI chip competitiveness. Current HBM3E stacks reach 12 layers, while future HBM4 could reach 16 layers, likely requiring hybrid bonding, especially for HBM4E. Limited advanced packaging capacity could tighten HBM4 availability.
The CoWoS capacity constraints impact hyperscalers and AI chip startups, prompting industry players to adopt strategies such as building alternative packaging lines and pursuing vertical integration. Vertical integration allows companies to control more stages from design to stacked manufacturing, improving supply chain resilience.
Overall, NVIDIA's early access to TSMC's cutting-edge A16 process, combined with its substantial CoWoS capacity reservations, sets a formidable barrier in next-generation AI chip competition. Other industry players will need innovative packaging solutions and vertical integration strategies to overcome supply constraints and compete in the AI computing market.