Samsung Unveils Sub-10nm DRAM Technology

On December 16, Samsung Electronics unveiled a breakthrough in DRAM technology at the 70th International Electron Devices Meeting in San Francisco. Its Samsung Advanced Institute of Technology (SAIT) announced the successful development of a novel transistor capable of supporting DRAM production below the 10nm process node, addressing a key challenge in mobile DRAM advancement.

The innovation, named the High-Heat-Resistant Amorphous Oxide Semiconductor Transistor for Sub-10nm CoP Vertical Channel DRAM, focuses on enabling DRAM processes under 10nm—a critical hurdle for mobile DRAM as traditional scaling approaches approach their physical limits.

Unlike conventional designs where peripheral circuits are placed beneath memory cells, Samsung's approach stacks the memory cells on top of the peripheral circuits, a method called Cell-on-Peri (CoP). This design prevents performance degradation that typically occurs when peripheral circuits are exposed to high-temperature stacking processes. To achieve this, Samsung employed a transistor based on amorphous indium gallium oxide (InGaO), which can withstand temperatures up to 550°C, preserving performance during manufacturing.

The vertical channel transistor features a 100nm channel length and is compatible with monolithic CoP DRAM architectures. During testing, the transistor showed minimal degradation in drain current and maintained stability under aging tests, highlighting its robustness.

Sources indicate that the technology is still in the research phase and is expected to be applied to 0a and 0b class DRAM below 10nm in the future. With its commercialization, Samsung aims to strengthen its position in the high-density memory market.