Cadence Tapes Out 3rd-Gen UCIe IP on TSMC N3P

Recently, Cadence announced that its third-generation Universal Chiplet Interconnect Express (UCIe) IP has successfully taped out on TSMC’s advanced N3P process. This milestone highlights an industry-leading per-lane data rate of up to 64 Gbps and lays a solid hardware foundation for the next wave of AI innovation.

As semiconductor manufacturing moves to 3nm and beyond, SoC designers face growing complexity. They must deliver fast and reliable die-to-die communication while tightly balancing power, performance, and area (PPA). Cadence positions its latest UCIe IP as a direct response to these challenges. Fully compliant with the UCIe specification and optimized for TSMC's N3P technology, the solution demonstrates strong power efficiency, enabling aggressive energy targets without sacrificing performance—an essential requirement for large, multi-chip systems that must operate reliably over time.

According to Cadence, the taped-out third-generation UCIe IP represents a major step forward in interconnect technology. With support for up to 64 Gbps per lane, designers can achieve extremely high bandwidth density, opening new possibilities for scalable chiplet architectures.

Performance scales impressively across packaging options. In standard packaging, bandwidth density reaches 3.6 Tbps/mm, while advanced packaging pushes that figure to as high as 21.08 Tbps/mm. Designed with AI and high-performance computing in mind, the architecture delivers best-in-class PPA, making it well suited for AI accelerators, networking hardware, and next-generation data center platforms.

To help shorten time to market and simplify integration, Cadence's UCIe IP emphasizes flexibility. It supports seamless connectivity with widely used protocols such as AXI, CXS.B, CHI-C2C, PCIe, and CXL.io. Combined with a complete high-speed PHY IP subsystem, this multi-protocol approach allows rapid deployment across a wide range of platforms. The design also prioritizes interoperability across multi-vendor chiplet ecosystems, ensuring stable operation in heterogeneous environments.

At the hardware level, the solution integrates advanced features such as error correction (ECC), lane margining, and diagnostic capabilities to maintain reliability under demanding workloads. Notably, it includes self-calibration and a hardware-based bring-up mechanism that removes the need for firmware intervention. This enables faster system initialization and simplifies overall setup. Paired with a streamlined clocking architecture that integrates PLLs, the system remains resilient to voltage and temperature variations, allowing engineers to focus more on core logic design.

Cadence's leadership in die-to-die interconnect IP has been built over several years. Arif Khan, Vice President of Marketing for Cadence's Silicon Solutions Group, noted that the company completed its first chip-to-chip interface IP tapeout as early as 2018. As industry momentum shifted, Cadence aligned with the UCIe standard in 2022 and has since demonstrated silicon-proven results from its first- and second-generation UCIe solutions over the past two years.