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Intel Fab 52 Hits 40K Wafers/Month, 18A Yield by 2027

2025-12-24 17:50:56Mr.Ming
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Intel Fab 52 Hits 40K Wafers/Month, 18A Yield by 2027

According to reports, Intel's Fab 52 facility is more advanced than TSMC's current Fab 21 Phase 1 and upcoming Phase 2 plants, with production capacity roughly equal to the combined output of both.

Fab 52 is designed to manufacture chips using Intel's cutting-edge 18A (1.8nm-level) and future process technologies. These processes leverage Gate-All-Around (GAA) RibbonFET transistors and the PowerVia backside power delivery network. At full capacity, the plant can process around 10,000 wafers per week, or roughly 40,000 wafers per montha scale that positions it among the largest semiconductor fabs today.

Currently, Fab 52 operates four ASML Twinscan NXE low-NA EUV lithography systems, including at least one NXE:3800Ethe most advanced low-NA EUV tool. This system incorporates wafer handling from next-gen high-NA EUV tools, faster wafer stages, and enhanced light sources, achieving up to 220 wafers per hour at a 30 mJ/cm² dose. The facility also houses three NXE:3600D systems capable of processing 160 wafers per hour at the same dose.

Intel has reserved space for at least 15 additional EUV machines at its Ocotillo "Silicon Desert" campus in Arizona, potentially introducing high-NA tools in the future to strengthen its technological lead.

Compared with TSMC Fab 21 Phase 1, which produces chips using N4 and N5 processes, Intel Fab 52 can run more advanced nodes down to 1.8nm and below, and its monthly wafer output is roughly double. However, despite this technological edge, Fab 52's mass production is limited by the yield ramp of the 18A process. The plant is currently in small-scale trial production of "Panther Lake" processors using 18A technology, but Intel expects yields to reach industry-leading levels only by early 2027. Until then, CPU production will remain constrained, and parts of the fab may operate below full capacity. By contrast, TSMC's U.S. fabs rely on mature processes and rapid scale-up, achieving near-full utilization much faster.

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