Samsung Plans 2nm Process for HBM4E

According to Korean media, Samsung Electronics is planning to apply a 2nm process to the base dies of its next-generation high-bandwidth memory (HBM), HBM4E. The company aims to launch standard HBM4E chips by mid-2026, with customized wafers entering production in the second half of the year based on specific customer requirements.

Since HBM4, the role of the base die has shifted dramatically—from purely handling control functions to performing certain computational tasks—significantly increasing its importance. To boost computing efficiency and energy management, its logic capabilities have been enhanced, driving a move toward more advanced semiconductor manufacturing processes.

Previously, Samsung implemented a 1c DRAM process for HBM4 and produced 4nm logic base dies through its own foundry, outpacing SK Hynix's HBM4 base dies, which used TSMC's 12nm process. As process nodes shrink further, base dies are seeing notable improvements in power efficiency, thermal management, and area utilization—laying the groundwork for fully customized HBM solutions.

Meanwhile, TSMC and SK Hynix are also advancing HBM4E customization. TSMC plans to introduce its latest 3nm process for tailored products, while SK Hynix is developing relevant technologies. Samsung's exploration of 2nm base dies is seen as a strategic move to maintain technological leadership in the HBM4E era.

Industry experts widely expect fully customized HBM to debut with HBM4E, marking a key milestone in the competitive AI semiconductor landscape.