TSMC CoWoS Tightens, Intel Eyes Packaging Orders

According to reports from South Korean media, Intel is increasingly being linked to potential opportunities involving orders traditionally associated with TSMC, as competition intensifies in advanced packaging for AI and high-performance computing applications.

The reports indicate that SK Hynix, a major global memory manufacturer with a leading position in high-bandwidth memory (HBM), has historically relied on TSMC’s CoWoS advanced packaging technology for AI chip integration. However, due to persistent capacity constraints in CoWoS production, SK Hynix is reportedly considering alternative packaging solutions, including Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology, for future 2.5D integration of HBM and logic chips such as GPUs.

Industry observers note that this potential shift reflects broader structural pressure across the semiconductor supply chain, where demand for AI servers, accelerators, and HBM continues to outpace advanced packaging supply. TSMC’s CoWoS capacity shortages have already become a key bottleneck for multiple leading AI chip designers, prompting exploration of alternative technologies.

Intel has recently been more active in promoting its advanced packaging portfolio. Beyond SK Hynix, international reports have suggested that several major technology companies are evaluating Intel’s foundry and packaging capabilities as part of efforts to diversify supply chain dependencies. This growing engagement signals Intel’s strategic push to strengthen its position in both advanced process and packaging markets under its broader foundry expansion strategy.

SK Hynix has maintained long-standing collaboration with TSMC in advanced packaging and has participated in initiatives such as TSMC’s 3D Fabric ecosystem. The two companies also signed a memorandum of understanding in 2024 to co-develop next-generation HBM technologies, including HBM4, highlighting previously close cooperation in next-generation memory integration.

However, recent Korean industry reports suggest that SK Hynix is actively evaluating Intel’s EMIB-based 2.5D packaging approach due to supply constraints at TSMC. Early-stage development discussions are reportedly underway, with SK Hynix testing EMIB-based integration schemes and exploring supporting materials required for potential mass production.

Analysts suggest that collaboration between SK Hynix and Intel could be mutually beneficial. For SK Hynix, diversified packaging options may improve supply stability, yield optimization, and system-level integration flexibility. For Intel, broader adoption of EMIB could significantly expand its footprint in the advanced packaging ecosystem, particularly in AI-related applications.

Market sources also indicate that Intel has been actively promoting EMIB technology to major chip developers and outsourced semiconductor assembly and test (OSAT) partners. In the medium to long term, EMIB is expected to become part of the broader 2.5D packaging supply chain for AI accelerators, alongside existing solutions.

Industry commentary further suggests that Intel’s advanced packaging yield has reportedly improved to over 90% in backend processes, which, while still trailing industry leaders, is considered sufficient for stable production scaling. Intel is also positioning its packaging roadmap around larger reticle-size designs to enable higher computational density at lower system cost.

Within its EMIB 2.5D roadmap, Intel is reportedly developing multiple variants, including EMIB-M, which integrates MIM capacitors within silicon bridges to enhance power delivery, and EMIB-T, which incorporates through-silicon via (TSV) structures to support design portability across different packaging architectures. These developments are intended to address future requirements for higher bandwidth memory integration and heterogeneous computing systems.

As competition in advanced packaging intensifies, the strategic dynamics among leading semiconductor players continue to evolve, with capacity, performance, and integration efficiency becoming key differentiators in the AI-driven chip ecosystem.