FuriosaAI to Use Broadcom 3.5D Packaging for AI Chip

According to The Register, leading semiconductor designer Broadcom Inc. has added South Korean AI chip startup FuriosaAI to its custom ASIC ecosystem partner program, with both companies collaborating to develop next-generation AI accelerators. Under the partnership, FuriosaAI will leverage Broadcom’s advanced packaging technologies to design its third-generation AI chip while integrating Broadcom’s networking and packaging solutions.

The collaboration focuses on integrating FuriosaAI’s Tensor Contraction Processor (TCP) technology into a multi-die System-on-Package (SoP) architecture, targeting high-demand large-scale AI inference workloads. Although detailed specifications of the upcoming chip remain limited, FuriosaAI stated that the design will be based on an advanced 2nm process node and will utilize Broadcom’s packaging capabilities to support a dual-layer HBM4 or HBM4E memory configuration.

Broadcom’s Extreme Dimension System-in-Package (3.5D XDSiP) technology is designed to simplify the development of complex chiplet-based AI accelerators, similar in concept to AMD’s MI300 series. The approach separates compute cores, memory, I/O, and supporting logic into distinct chiplets, which are then reassembled using advanced 3D packaging techniques such as hybrid bonding. Compared to building a monolithic SoC from scratch, this modular method allows chip designers to focus on core compute innovation while significantly reducing development time, capital expenditure, and product risk.

In addition to packaging innovations, FuriosaAI’s third-generation accelerator is expected to incorporate Broadcom Ethernet and PCIe technologies to enable large-scale multi-chip systems supporting more than eight chips, surpassing the limitations of its current architecture. The system may also adopt Broadcom’s Tomahawk 6 (TH6) switch, enabling both traditional scale-out networking and high-density scale-up configurations.

This latest partnership comes roughly one year after FuriosaAI previewed its second-generation RNGD AI accelerator, a PCIe-based card positioned closer to high-end workstation GPUs or earlier-generation data center accelerators rather than today’s most advanced AI chips.

In its preview materials, FuriosaAI showcased a third-generation AI chip design featuring 12 HBM4/HBM4E memory stacks, two large compute chiplets built on a 2nm process, and two I/O controllers. With 36 GB per stacked 12-high memory module, total memory capacity could reach up to 432 GB.

Notably, Meta Platforms Inc. has previously relied on Broadcom for the design of several AI accelerator products within its MTIA lineup, while Google LLC’s latest TPU v8 series is also reported to involve Broadcom’s design support. Custom AI accelerator development has therefore become a major growth engine for Broadcom, accounting for approximately 65% of its total revenue in the first fiscal quarter of FY2026.