TSMC Starts CoPoS Pilot Production

According to recent supply chain reports, surging demand for AI accelerators is placing unprecedented pressure on advanced semiconductor packaging capacity, prompting Taiwan Semiconductor Manufacturing Company (TSMC) to accelerate development of its next-generation CoPoS (Chip-on-Panel-on-Substrate) packaging platform. The company has reportedly secured key materials and consumables for the project and has begun comprehensive validation of production equipment and manufacturing lines.

CoPoS is widely viewed as a panel-level evolution of TSMC’s industry-leading CoWoS (Chip-on-Wafer-on-Substrate) packaging technology. Unlike conventional CoWoS processes that rely on circular silicon interposers, CoPoS utilizes square glass or organic panels. This transition significantly improves substrate utilization by reducing wasted edge space. While traditional 12-inch wafers achieve utilization rates of roughly 65% when accommodating square AI chips, panel-based packaging can increase utilization to approximately 95%.

The efficiency gains are particularly significant for large AI processors. Using NVIDIA’s B200 accelerator as an example, a square panel can accommodate between 9 and 16 chip sets within the same area where only four sets could be packaged on a conventional wafer. This enables substantial increases in output while reducing material waste and manufacturing costs.

Another major advantage of CoPoS is scalability. The technology supports panel sizes beyond the limitations of traditional 300 mm wafers, with formats such as 310 × 310 mm, 515 × 510 mm, and even 750 × 620 mm under consideration. These larger dimensions are expected to provide a critical foundation for future generations of ultra-large high-performance computing (HPC) and AI chips.

TSMC’s push toward CoPoS is driven by the need to overcome both capacity constraints and technical limitations facing existing packaging technologies. Industry sources indicate that even if CoWoS production capacity expands to 130,000 wafers per month by the end of 2026, fulfillment rates may still remain around 80% due to overwhelming customer demand. At the same time, increasing AI computing requirements are driving chip package sizes closer to reticle limits, creating new challenges for conventional advanced packaging approaches.

During TSMC’s annual shareholders’ meeting on June 4, Chairman and CEO C.C. Wei publicly confirmed progress on the company’s CoPoS pilot production line. He noted that the technology requires extensive customer collaboration, process optimization, and yield improvement before commercial deployment. Large-scale mass production is expected to remain two to three years away.

Supply chain sources further indicate that TSMC has established its first CoPoS pilot line at the Longtan facility operated by its subsidiary VisEra Technologies. The company aims to begin limited-volume production between the second half of 2026 and 2027 while continuing technology verification and process refinement.

With key materials now in place, equipment qualification and production-line validation activities are accelerating. Initial equipment suppliers reportedly include global semiconductor manufacturing leaders such as Tokyo Electron and Applied Materials, alongside more than a dozen Taiwan-based equipment vendors. These companies support critical process stages including wet processing, automation systems, thermal treatment, and automated optical inspection, leveraging expertise gained through the existing CoWoS ecosystem.

Despite its advantages, transitioning from circular wafers to square panels introduces significant engineering challenges. Square substrates are more susceptible to stress concentration, thermal expansion mismatch, and warpage. Furthermore, most semiconductor manufacturing equipment was originally designed for circular wafer handling, meaning hundreds of process steps may require redesign and requalification. Any defect on a large panel can also impact the yield of multiple chips simultaneously, placing greater demands on inspection, metrology, and cleaning technologies.

Nevertheless, industry observers believe the steady progress of validation activities demonstrates that TSMC is gradually overcoming these obstacles. Reports suggest that NVIDIA, currently the largest CoWoS customer, could become one of the first companies to adopt CoPoS packaging. Other major semiconductor firms, including Advanced Micro Devices and Broadcom, are also expected to evaluate and potentially deploy the technology.

For future capacity expansion, TSMC has designated the P4 and P5 facilities at its AP7 site in Chiayi as the primary mass-production base for CoPoS. Large-scale manufacturing is expected to begin between late 2028 and 2029. The company is also reportedly planning advanced packaging capacity based on the technology at its Arizona operations in the United States.

Industry analysts view glass-panel packaging as a key enabler for the next phase of AI chip scaling and packaging density improvements. Many expect 2026 to mark the beginning of commercial adoption, with substantial capacity expansion and broader industry deployment anticipated after 2028 as demand for advanced AI processors continues to grow.