TSMC PLP Mass Production in 2027, Challenges Samsung

According to industry sources on June 15, TSMC is preparing to compete head-on with Samsung Electronics by advancing a next-generation semiconductor packaging technology known as Panel Level Packaging (PLP).

Insiders report that TSMC is actively building a complete PLP production ecosystem, including materials, components, and equipment supply chains. The company is also in discussions with global partners regarding equipment investments. Mass production is expected to begin as early as next year, marking a significant step toward commercializing the technology at scale.

PLP refers to a packaging process in which fabricated semiconductor wafers are diced into individual dies and then reassembled on a rectangular panel for final packaging. This approach contrasts with conventional Wafer Level Packaging (WLP), which uses circular wafers.

Because circular wafers leave unused edge areas during processing, material utilization is inherently limited. By switching to square or rectangular panels, PLP significantly reduces waste and improves chip yield. For example, a 600×600mm panel can deliver roughly five to six times the output of a standard 300mm (12-inch) wafer.

Samsung Electronics is currently regarded as a pioneer in PLP technology. Since taking over PLP operations from Samsung Electro-Mechanics in 2019, the company has applied the technology to mobile application processors (APs) and power management ICs (PMICs), steadily accumulating process expertise.

In contrast, TSMC has traditionally focused on wafer-level packaging technologies, maintaining a more cautious approach toward PLP. However, rapid growth in the artificial intelligence (AI) chip market has shifted its strategy. The company formally initiated its PLP program in 2024.

Industry expectations suggest that TSMC will complete its pilot production line this year, followed by performance validation, before moving into full-scale mass production in 2027. Reports also indicate that TSMC has already secured order commitments from global AI chip customers.

As TSMC accelerates PLP development, competition with Samsung Electronics is expected to intensify further. Samsung is also planning to extend its PLP applications beyond APs and PMICs into high-performance computing (HPC) and AI chips.

In addition, glass substrates—considered a key material for next-generation AI chips—are also expected to be integrated with PLP processes in the future. This development could further heighten competition between the two companies in advanced packaging technologies.

Industry observers note that it is not only Samsung and TSMC entering this field, but also a growing number of outsourced semiconductor assembly and test (OSAT) companies actively positioning themselves in the PLP market. As competition intensifies, the overall market size is expected to expand rapidly.