TSMC Joins imec & ASML on 2D Wafer Tech

According to announcements from industry partners, imec, ASML, and TSMC are jointly advancing a new 12-inch wafer integration roadmap aimed at accelerating the development of two-dimensional (2D) material-based field-effect transistors (FETs).

The collaboration focuses on establishing a scalable and robust integration pathway for both n-type and p-type FET architectures using 2D materials. The initiative represents a significant step toward transitioning 2D transistor research from laboratory demonstrations to wafer-scale manufacturing environments, strengthening the long-term technology pipeline for advanced semiconductor nodes.

The newly presented platform demonstrates miniaturized nFETs and pFETs built on a 12-inch wafer process with a 50 nm gate pitch (CPP). The n-type devices utilize molybdenum disulfide (MoS₂) as the channel material, while the p-type devices are based on tungsten diselenide (WSe₂) or tungsten disulfide (WS₂). Experimental results show promising current–voltage (I–V) characteristics, indicating stable device behavior at highly scaled dimensions.

According to imec, this achievement marks a key milestone in enabling 2D material transistors to move beyond experimental prototypes toward potential integration in advanced semiconductor manufacturing. The platform is designed to support extreme device scaling for future logic technologies, as well as back-end-of-line (BEOL) and backside integration applications.

TSMC leadership noted that the collaboration provides important momentum for semiconductor innovation by reducing the risks associated with transferring emerging materials from research environments into production-grade processes. The focus is on accelerating the integration of novel channel materials into advanced manufacturing flows, enabling faster adoption of next-generation device architectures.

Industry observers suggest that 2D transition metal dichalcogenides (TMDs)—including MoS₂, WS₂, and WSe₂—could extend the scaling roadmap beyond current silicon limitations. When implemented as atomically thin channel materials, these compounds offer strong potential for continued transistor scaling, supporting future logic nodes beyond the A10 (1 nm-class) era.

Overall, the joint development highlights a coordinated effort across leading semiconductor ecosystem players to explore post-silicon materials and maintain long-term scaling momentum in advanced logic technologies.