Samsung Advances Vertical Stacking for Logic Chips

According to Samsung Electronics, the company is accelerating the development of next-generation semiconductors by applying vertical stacking technology to logic (system-on-chip) devices.

Samsung Electronics announced on June 17 that researchers at its Semiconductor R&D Center have, for the first time globally, demonstrated a three-dimensional (3D) stacked transistor structure with a 42nm gate pitch. The achievement was recently recognized with a Best Paper Award at the 2026 VLSI Symposium held in Kyoto, Japan.

The breakthrough is significant because it extends vertical stacking—previously used mainly in memory semiconductors—into the field of logic devices. In NAND flash, Samsung has already pushed storage density limits through V-NAND technology, while in DRAM it has led the high-bandwidth memory (HBM) market, which is critical for artificial intelligence (AI) workloads.

According to Samsung Semiconductor R&D Center researcher Kwon Wook-hyun, vertical integration represents a natural evolution in semiconductor scaling. “Looking back at decades of development, we have overcome area limitations through vertical structures. V-NAND in NAND flash and HBM in DRAM are key examples, and this trend is now extending to logic semiconductors,” he said.

Traditional logic chips increase integration by placing transistors side by side on a planar surface. However, as device spacing shrinks, electromagnetic interference becomes increasingly difficult to control, limiting further miniaturization. As a result, the industry is actively exploring 3D architectures that stack devices vertically to improve performance and density.

Samsung Semiconductor R&D Center CTO Jung Young-chae explained that shrinking transistor spacing also weakens insulating layers. “When insulation thickness falls below a certain threshold, its effectiveness can be lost,” he said. “By placing devices vertically, horizontal constraints can be removed—similar to how a neighborhood of single houses evolves into multi-story mixed-use buildings.”

Using this approach, Samsung’s research team achieved a 42nm gate pitch, narrower than the current industry benchmark of 48nm. The researchers also introduced a novel structure that directly connects vertically stacked transistors, further improving integration density.

Kwon noted that “42nm represents the smallest transistor pitch demonstrated in the industry to date,” adding that the direct vertical connection between transistors was achieved for the first time.

Looking ahead, Samsung researchers expect the technology to strengthen semiconductor competitiveness in AI and high-performance computing (HPC) applications.

According to senior researcher Hwang Dong-hoon from Samsung Semiconductor R&D Center, “Vertical stacking allows more transistors to be placed in the same area. This architecture is well suited to meet AI-era demands for smaller chip area, lower power consumption, and higher performance.”