Intel Wins Google TPU Order

According to recent reports citing research firm SemiAnalysis, Google is expected to adopt Intel’s EMIB-T advanced packaging technology for its next-generation Tensor Processing Unit (TPU), replacing the TSMC CoWoS packaging technology used in previous TPU generations.

The report indicates that Google's upcoming TPU, codenamed Humufish, will be packaged using Intel's latest EMIB-T (Embedded Multi-die Interconnect Bridge with Through-Silicon Via) technology instead of TSMC's industry-leading CoWoS (Chip-on-Wafer-on-Substrate) platform. If confirmed, the move would represent a significant milestone for Intel Foundry's advanced packaging business and one of its most notable AI-related packaging wins.

Neither company has confirmed the report. TSMC declined to comment on market rumors or customer-specific business matters, while Intel also declined to provide any official response.

Industry observers believe one factor behind the reported shift could be the continued tight supply of TSMC's CoWoS capacity. As demand for AI accelerators continues to surge, CoWoS production has remained heavily booked by major AI chip developers, creating opportunities for alternative advanced packaging technologies to gain traction.

TSMC's CoWoS has become the dominant packaging platform for AI GPUs and AI accelerators, supporting products from leading chip developers including NVIDIA, AMD, and multiple hyperscale cloud service providers. However, SemiAnalysis stated in a post on X that Google's next-generation TPU will instead utilize Intel's EMIB-T technology.

Beyond capacity considerations, the reported transition also reflects a broader trend among hyperscale cloud companies to diversify their semiconductor supply chains. Establishing a second source for advanced packaging can improve supply resilience while potentially offering advantages in manufacturing cost and production flexibility.

At the same time, analysts note that Intel's EMIB-T remains a relatively new manufacturing technology. Its success will depend on Intel's ability to achieve high manufacturing yields and ramp production on schedule. Any significant delays could still leave the door open for Google to return to TSMC's packaging ecosystem.

TSMC currently offers several CoWoS variants designed for different high-performance computing applications. CoWoS-S utilizes a silicon interposer to deliver high-density interconnects for heterogeneous chip integration, although interposer size is limited to approximately 3.3 times the reticle size. CoWoS-R employs a redistribution layer (RDL) interposer to connect system-on-chip (SoC) devices with high-bandwidth memory (HBM), while CoWoS-L combines RDL technology with embedded Local Silicon Interconnect (LSI) to support larger, next-generation HPC and AI devices.

Intel's EMIB 2.5D packaging architecture takes a different approach by replacing a large silicon interposer with compact silicon bridges and advanced multilayer routing while still supporting HBM integration. The company positions the technology as a highly efficient solution for AI and high-performance computing workloads.

According to Intel's previously released technical information, its advanced EMIB platform is expected to support package sizes ranging from eight to ten times the reticle size while delivering high compute density at lower cost. The latest EMIB-T version further incorporates Through-Silicon Via (TSV) technology, enabling greater design flexibility and compatibility with multiple advanced packaging approaches.