Samsung HBM5 Targets 2x Performance, 20% Efficiency Gain

According to Samsung Electronics executives speaking at the recent Memory Executive Summit in Taipei, the company is targeting a major performance leap with its next-generation HBM5. Samsung aims to double peak performance compared with HBM4E, while improving performance per watt by 20% and reducing thermal resistance by 20%.

Choi Jang-seok, head of product planning for Samsung Electronics’ Memory Business, said HBM5 will be the company’s eighth-generation high-bandwidth memory. The base die is expected to use Samsung’s 2nm foundry process, an upgrade from the 4nm process used for HBM4 and HBM4E. Samsung is also preparing 12-layer, 16-layer, and 20-layer DRAM stacking configurations.

To improve thermal management, HBM5 will feature a Heat Path Block (HPB) designed to reduce thermal resistance and simplify cooling. Samsung expects HBM5 mass production to begin around 2028.

The key challenge is how Samsung will achieve its targeted bandwidth increase. HBM4E is generally associated with a data rate of around 12 GT/s and a 2,048-bit interface. Doubling bandwidth could involve significantly increasing signaling speed, widening the interface, or adopting a combination of both. A wider interface can improve energy efficiency but also increases TSV, I/O, bump, routing, and base-die design complexity.

Samsung’s HBM5 roadmap is part of its broader CUBE (Capacity, Utilization, Bandwidth, Efficiency) strategy. The company also unveiled its longer-term zHBM concept, which would directly stack HBM on logic processors such as GPUs or CPUs. Samsung targets up to eight times the performance of HBM4E, three times the performance per watt, and a 75%–90% reduction in thermal resistance.

With AI accelerators demanding increasingly higher memory bandwidth, Samsung’s HBM5 and zHBM technologies highlight the company’s efforts to strengthen its position in the next generation of AI memory and advanced semiconductor packaging.