TSMC to Produce Chip Twice Today's Largest Size

TSMC recently made a significant announcement at a North America technology symposium regarding the development of a new version of its CoWoS (Chip-on-Wafer-on-Substrate) packaging technology. This advancement is set to more than double the size of system-in-package (SiP) designs. The foundry anticipates that these new packages could reach dimensions of 120 x 120 mm and consume several kilowatts of power.

The latest iteration of CoWoS enables TSMC to manufacture silicon interposers approximately 3.3 times larger than traditional mask sizes (858 square mm). This offers enhanced capacity for integrating logic, eight HBM3/HBM3E memory stacks, I/O, and other chiplets across a surface area of up to 2,831 square mm. The maximum board size for these packages is 80 x 80 mm. AMD’s Instinct MI300X and NVIDIA’s B200 already utilize this technology, with the B200 chip being larger than AMD’s MI300X.

The next generation of CoWoS_L, set to begin production in 2026, will expand interposer size to about 5.5 times the mask size (slightly less than the previously announced 6 times). This will allow for 4,719 square mm of space for logic, up to 12 HBM memory stacks, and other chiplets. Larger substrates will also be required; according to TSMC’s projections, a 100 x 100 mm board is under consideration. These chips will not be compatible with OAM modules.

TSMC has more developments in store. By 2027, it plans to introduce a new version of CoWoS technology that will expand interposer size to 8 times or more the mask size, providing up to 6,864 square mm of space for chiplets. One envisioned design relies on four stacked system-on-integrated-chip (SoIC) units, paired with 12 HBM4 memory stacks and additional I/O chips. These advanced solutions are also expected to utilize a 120 x 120 mm board.

Earlier this year, Broadcom showcased a custom AI chip featuring two logic chips and 12 HBM memory stacks. The exact specifications of this product are not yet publicly available, but it appears to be larger than AMD's Instinct MI300X and NVIDIA's B200, although not as large as TSMC's plans for 2027.