Alphawave Unveils 64 Gbit/s UCIe with 3nm Interconnect

Alphawave Semi, a leading semiconductor IP company based in Canada, has recently showcased the world's first 64 Gbit/s Die-to-Die (D2D) IP subsystem designed for Universal Chiplet Interconnect Express (UCIe) technology.

This third-generation chiplet interconnect IP is set to be built using TSMC's cutting-edge 3nm process technology, leveraging TSMC's advanced packaging techniques and industry standards. It is based on the latest Gen2 36 Gbit/s and Gen1 24 Gbit/s implementations, also utilizing TSMC's 3nm process. The high bandwidth interconnect provides over 20 Tbit/s/mm bandwidth density, offering significant advantages in low power consumption and low latency.

The IP is highly configurable and supports multiple protocols, including AXI-4, AXI-S, CXS, CHI, and CHI-C2C, addressing the growing demand for high-performance connectivity in applications such as High-Performance Computing (HPC), data centers, and artificial intelligence (AI).

Compliant with the latest UCIe specifications, the IP features a scalable architecture with advanced testability functions, including real-time channel health monitoring. This D2D interconnect solution is designed to facilitate a range of both established and emerging chiplet connection scenarios. Common use cases include linking compute chiplets for low-latency, consistent connectivity via UCIe's streaming functionality, and connecting compute to I/O chiplets through UCIe interfaces with PCIe, CXL, or Ethernet.

To enhance system connectivity, optical retimers are employed to create reliable, low-latency optical I/O links via optical engines. This supports the development of low-power, high-speed solutions in data centers and AI/ML systems.

For high-performance applications, the creation of custom HBM-based chips using the latest UCIe standards represents a groundbreaking approach. It involves tightly integrating memory chips with compute chips to achieve ultra-high bandwidth and low-latency communication between components. This method optimizes memory transactions, especially in AI applications, by reusing the die-to-die interfaces already present on the main chip for kernel-to-kernel or kernel-to-I/O connectivity.

Brian Rea, Chair of the UCIe Alliance Marketing Working Group, stated, “The UCIe Alliance is thrilled to see our members reaching key milestones, such as successful tape-outs, reflecting the growing adoption of UCIe standards. UCIe is the cornerstone of the chiplet industry, providing robust solutions for high-speed, low-latency die-to-die interconnects. By embracing open standards, we enable the industry to accelerate innovation, shorten time-to-market, and deliver breakthrough technologies.”

Mohit Gupta, Senior Vice President and General Manager of Alphawave Semi, added, “We've successfully taped out Gen2 UCIe IP at 36 Gbit/s using 3nm technology, building upon our pioneering silicon-validated 3nm UCIe IP with CoWoS packaging. This sets the stage for our 64 Gbit/s Gen3 UCIe IP, which aims to deliver high-performance, 20 Tbit/s/mm throughput capabilities to meet the critical AI bandwidth demands of our customers by 2025.”