Intel Unveils Clearwater Forest Xeon 6+: 288 Cores

On October 9, Intel unveiled its third-generation Core Ultra processors, codenamed Panther Lake, marking the first client SoC built on Intel's 18A process. At the same time, Intel previewed its next-gen Xeon 6+ server processor, Clearwater Forest, also based on the 18A process. Both chips are currently being manufactured at Intel's state-of-the-art Fab 52 in Chandler, Arizona. Panther Lake is expected to ship by the end of this year, while Clearwater Forest is slated for release in the first half of 2026.

Clearwater Forest represents Intel's new high-efficiency core design for servers. Leveraging the 18A process, it is among Intel's most energy-efficient server CPUs to date. The processor can host up to 288 efficiency cores, achieving a 17% boost in instructions per cycle (IPC) over the previous generation, while delivering significant gains in density, throughput, and energy efficiency—ideal for hyperscale data centers, cloud providers, and telecom operators.

Built on a chiplet architecture, Clearwater Forest integrates multiple tiles using Intel's advanced Foveros Direct 3D packaging technology. This solution bridges Compute Tiles and I/O Tiles on a base tile, using a dense 9 µm bump pitch and copper-to-copper bonding for low-resistance, high-density connections. This allows nearly zero energy cost for data transfer between tiles.

The chip integrates 12 Compute Tiles (18A process), 3 Active Base Tiles (Intel 3 process), 2 I/O Tiles (Intel 7 process), and 12 EMIB Tiles. Each Compute Tile includes six modules, each with four new Darkmont E cores, totaling 24 cores per tile. Across 12 Compute Tiles, the processor packs 288 Darkmont E cores and 288 MB of L2 cache, contributing to an overall 864 MB of L2+L3 cache.

Each I/O Tile houses eight accelerators split into two groups, supporting Intel’s Quick Assist Technology, Dynamic Load Balancer, Data Flow Accelerator, and Memory Analytics Accelerator. Connectivity includes 48 PCIe Gen 5.0 lanes per I/O Tile (96 lanes total), 32 CXL 2.0 lanes per tile (64 lanes total), and 96 UPI 2.0 lanes (192 total), surpassing the previous Sierra Forest generation.

The Base Tiles connect to the Compute Tiles via EMIB technology and include four DDR5 memory controllers each, giving Clearwater Forest a total of 12 memory channels. Each Base Tile also carries a shared LLC of 48 MB per Compute Tile or 192 MB per Base Tile, totaling 576 MB on-package LLC.

Intel's data shows Clearwater Forest achieves leading performance per watt. Compared to the unreleased 288-core Xeon 6900E "Sierra Forest," it delivers 1.3× performance per watt. Against the 144-core 330W Sierra Forest (Xeon 6780E), Clearwater Forest doubles core count while reducing TDP by 36.3%, boosting total performance by 112.7% and performance-per-watt by 54.7%. Compared to a 500W 288-core Sierra Forest, Clearwater Forest at 450W achieves 17% higher performance and 30% better efficiency per watt.

In summary, Clearwater Forest combines Intel's new Darkmont E cores with advanced packaging to deliver 17% higher IPC, 1.9× overall performance, 23% better efficiency, and an 8:1 server integration ratio, setting a new benchmark for high-efficiency, high-performance server processors.