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Nvidia Set to Lead TSMC A16 Process Launch

2025-12-03 14:45:08Mr.Ming
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Nvidia Set to Lead TSMC A16 Process Launch

According to overseas media Wccftech and people familiar with the supply chain, Nvidia is very likely to become the first customer for TSMC's next-generation A16 (1.6nm) process, with its next-next-gen GPU code-named "Feynman" expected to debut on this node. At present, Nvidia is also the only company rumored to be lining up for A16, highlighting just how closely its roadmap is tied to TSMC's most advanced manufacturing plans.

According to the report, Nvidia's upcoming Rubin and Rubin Ultra GPU families will stick with a 3nm process first, before the company makes a major leap directly to A16 with the Feynman generation. Based on Nvidia's own product roadmap, Vera Rubin is expected to arrive in the second half of 2026, Rubin Ultra in the second half of 2027, and Feynman around 2028, setting a clear timeline for the industry's move into 1.6nm-class production.

To support this plan, TSMC is speeding up construction of its Kaohsiung P3 facility, which is scheduled to begin mass production of A16 around 2027. At the same time, TSMC's recent expansion of 3nm capacity is widely seen in the industry as preparation for Nvidia's strong near-term demand while laying the groundwork for the shift to A16.

Technically, TSMC's A16 process will use a nanosheet transistor structure together with Super Power Rail (SPR) backside power delivery. This design frees up more front-side routing space, increases logic density, and reduces voltage drop. The backside contact approach also keeps traditional layout flexibility, marking an industry-first integrated backside power solution. Compared with the N2P node, A16 is said to deliver 8–10% higher performance at the same power, or cut power by 15–20% at the same speed, while boosting density to 1.10× — features that are especially attractive for AI and high-performance computing chips.

Finally, TSMC is not alone in pushing backside power technology. Samsung has announced that its SF2Z process with BSPDN (Backside Power Delivery Network) will enter mass production in 2027, while Intel plans to introduce its PowerVia architecture with the Intel 18A node in late 2025. Together, these moves signal that backside power is quickly becoming a core technology in the race beyond 2nm.

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