Samsung 10a DRAM Targets 2028 Production
According to industry reports, the development of advanced DRAM process nodes below the 10-nanometer class is becoming increasingly challenging as memory manufacturers continue to push the limits of scaling technology.
According to The Elec, Samsung Electronics successfully completed pilot wafer production using its 10a DRAM process in March this year. Device-level testing confirmed that the chips operate normally, marking a key milestone in next-generation memory development.
The report highlights that this is the first industry implementation combining a 4F square-cell architecture with vertical channel transistor (VCT) technology. Under Samsung’s roadmap, the company aims to complete full development of 10a DRAM in 2026, begin quality validation in 2027, and move toward mass production in 2028.
Samsung also plans to apply the 4F cell structure and VCT architecture across three consecutive DRAM generations—10a, 10b, and 10c nodes. Starting from the 10d node, the company is expected to transition toward a full 3D DRAM technology roadmap.
In industry terminology, DRAM nodes below 10nm typically follow a naming sequence such as 1x, 1y, 1z, 1a, 1b, 1c, and 1d, with 10a representing the next generation after 1d. It is considered the first sub-10nm DRAM process, with an estimated effective feature size of approximately 9.5–9.7nm.
Currently, mainstream commercial DRAM uses a 6F square-cell structure, where “F” refers to the minimum lithographic feature size. The new 4F architecture adopts a 2F × 2F layout, significantly improving area efficiency. Under the same die size, cell density can increase by 30% to 50%, making it a key enabler for continued DRAM scaling.
The 4F structure is enabled by VCT technology, which vertically stacks the storage capacitor above the transistor, further reducing cell footprint. Peripheral circuits traditionally placed around the memory array are fabricated on a separate wafer and then integrated using wafer bonding under a periphery-under-cell (PUC) architecture.
One of the major technical challenges in this transition lies in material replacement. Samsung Electronics has replaced silicon channel materials with indium gallium zinc oxide (IGZO), improving leakage control and data retention performance at smaller geometries. However, word-line materials are still under evaluation.
The company initially considered molybdenum as a replacement for titanium nitride due to its lower resistivity and potential elimination of barrier layers. However, molybdenum introduces significant manufacturing challenges, including corrosion issues and complex process integration requirements, which would require substantial modifications to gas delivery systems, piping, and process control infrastructure.
Beyond Samsung, other major memory players are also accelerating development of 4F cell structures and VCT-based technologies. Reports indicate that SK Hynix is not expected to adopt the 10a node and instead plans to introduce this architecture at the 10b process stage.
However, the 4F vertical gate platform requires peripheral logic circuitry to be manufactured using logic process nodes. As SK Hynix does not operate an in-house 12-inch logic fabrication line, it is evaluating two options: building its own capacity or outsourcing production to external foundries. Given limited foundry capacity, reliance on external manufacturing may present constraints for large-scale adoption.
