TSMC COUPE Targets 4 Tbps by 2030

According to TSMC Advanced Packaging R&D Director Yen-Ming Chen, semiconductor scaling is shifting from single-chip system-on-chip (SoC) integration toward system-level scaling as AI workloads continue to expand. Speaking at the “Global Summit on Heterogeneous Integration” during SEMICON Taiwan 2026, Chen outlined how TSMC is using advanced logic, 3D stacking, silicon photonics, and advanced packaging technologies to address the growing challenges of computing performance, bandwidth, power delivery, and thermal management.

Chen said AI computing requirements are increasing by roughly four to five times annually, driven by the rapid development of large language models (LLMs), multi-step reasoning, and agentic AI systems. To meet these demands, TSMC is developing a technology roadmap spanning advanced process nodes, SoIC 3D stacking, COUPE silicon photonics, and CoWoS advanced packaging.

At the process level, TSMC’s N2 technology has entered production, while future A16 and A14 nodes are expected to advance semiconductor scaling into the angstrom era. Its SoIC 3D stacking technology is also moving toward tighter interconnect pitches, with a 4.5-micron A16 SoIC solution planned for volume production in 2029.

Memory and interconnect bandwidth are also being scaled. With an advanced logic base die, HBM4 using an N12 process could reduce power consumption by about 45% while increasing bandwidth by 2.5 times. Future HBM5 is expected to adopt an N3-based base die. Meanwhile, reducing the SoIC pitch to 4.5 microns could deliver up to four times higher bandwidth density.

For optical connectivity, TSMC’s first-generation COUPE platform is scheduled for volume production in 2026, with a long-term goal of reaching up to 4 Tbps of transmission bandwidth by 2030. Integrating optical technologies directly into an interposer could further improve energy efficiency.

TSMC is also expanding CoWoS packaging to support increasingly large AI systems. In 2026, the company began volume production of a CoWoS package reaching 5.5 times reticle size, with yields remaining above 90%. A 9-times-reticle-size platform is planned for 2027, with future solutions expected to exceed 14 times reticle size. From 2024 to 2029, the number of transistors within a system is projected to increase by about 14 times, while memory bandwidth could rise by more than 34 times.

As total power consumption within a single package is expected to increase significantly, system-technology co-optimization (STCO) will become increasingly important for power delivery and thermal management. TSMC is integrating high-density deep trench capacitors (DTCs) into interposers, with a reported density of up to 1,000 μF/mm², while integrated voltage regulators (IVRs) can help reduce impedance and voltage droop.

Thermal management is also evolving toward liquid cooling. TSMC has reduced the thermal resistance of CoWoS systems by about 40% and is working with ecosystem partners on future TIM-less cooling technologies. One potential approach is to create microchannels directly on the back of chips to improve heat removal and reduce thermal resistance.

Chen emphasized that advanced AI systems require a broad ecosystem spanning chip design, EDA, memory, packaging, and substrates. TSMC’s 3Dblox modular design language entered the IEEE standardization process in 2025, while its 3DFabric Alliance brings together industry partners to improve 3D IC design and support the development of next-generation AI computing systems.